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71M6543F/71M6543G Data Sheet
Table 50: Data/Direction Registers for SEGDIO51 to SEGDIO55
SEGDIO
51
52
53
54
55
Pin #
53
52
51
47
46
–
–
–
Configuration:
0 = DIO, 1 = LCD
3
4
5
6 7 –
LCD_MAP[55:48]
(I/O RAM 0x2405)
–
–
SEG Data Register
51 52 53 54 55 – – –
LCD_SEGDIO51[5:0] to LCD_SEGDIO55[5:0]
(I/O RAM 0x2443[5:0] to 0x2447[5:0])
DIO Data Register
Direction Register:
0 = input, 1 = output
51
51
52 53 54 55 – –
LCD_SEGDIO51[0] to LCD_SEGDIO55[0]
(I/O RAM 0x2443[0] to 0x2447[0])
52 53 54 55 – –
LCD_SEGDIO51[1] to LCD_SEGDIO55[1]
(I/O RAM 0x2443[1] to 0x2447[1])
–
–
2.5.10.3 LCD Drivers
The LCD drivers are grouped into up to six commons (COM0 – COM5) and up to 56 segment drivers.
The LCD interface is flexible and can drive 7-segment digits, 14-segment digits or enunciator symbols.
A voltage doubler and a contrast DAC generate VLCD from either VBAT or V3P3SYS, depending on the
V3P3SYS voltage. The voltage doubler, while capable of driving into a 500 kΩ load, is able to generate a
maximum LCD voltage that is within 1 V of twice the supply voltage. The doubler and DAC operate from
a trimmed low-power reference.
The configuration of the VLCD generation is controlled by the I/O RAM field LCD_VMODE[1:0] (I/O RAM
0x2401[7:6]) . It is decoded into LCD_EXT, LDAC_E, and LCD_BSTE . Table 51 details the
LCD_VMODE[1:0] configurations.
Table 51: LCD_VMODE Configurations
LCD_VMODE[1:0] LCD_EXT LDAC_E LCD_BSTE Description
11
10
01
1
0
0
0
1
1
0
1
0
External VLCD connected to the VLCD pin.
LCD boost is enabled. Maximum VLCD voltage is
2*V3P3L-1.
VLCD = max(2*V3P3L-1, 2.65(1+ LCD_DAC[4:0] /31)
LCD boost is disabled. The maximum VLCD
voltage is V3P3L.
VLCD = max(V3P3L, 2.65(1+ LCD_DAC[4:0] /31)
VLCD=V3P3L, the LCD DAC and LCD boost are dis-
00 0 0 0 abled. In LCD mode, this setting causes the lowest
battery current.
Notes:
1. LCD_EXT, LDAC_E and LCD_BSTE are 71M6543 internal signals which are decoded from
the LCD_VMODE[1:0] control field setting ( I/O RAM 0x2401[7:6] ). Each of these decoded signals,
when asserted, has the effect indicated in the description column above, and as summarized
below.
LCD_EXT : When set, the VLCD pin expects an external supply voltage
LDAC_E : When set, LCD DAC is enabled
LCD_BSTE : When set, the LCD boost circuit is enabled
2. V3P3L is an internal supply rail that is supplied from either the VBAT pin or the V3P3SYS pin,
depending on the V3P3SYS pin voltage. When the V3P3SYS pin drops below 3.0 VDC, the
71M6543 switches to BRN mode and V3P3L is sourced from the VBAT pin, otherwise V3P3L
is sourced from the V3P3SYS pin while in MSN mode.
v2
61
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